Low-energy computing

Low-energy computing requires that the power demands are on par with energy that can be harvested from the environment. In practice, only a few mW may be available for sensing, communications, and computing. In this domain we investigate energy efficient fully programmable architectures and high-level design tool chains.



Professor Olli Silvén


Selected research: Transport Triggered Architecture (TTA) applications


Industrial condition monitoring

We have studied energy efficient signal processing methods for condition monitoring of various industrial applications. We have implemented methods on the transport triggered architecture (TTA) signal processor in order to achieve performance and energy efficiency needed by energy autonomous wireless sensor nodes. The sensor node implemented together with VTT is illustrated in figure below. Our TTA signal processor was implemented on the Flash FPGA on the node.

Application specific accelerator for computer vision

The research of energy efficient signal processing methods has also expanded to cover future IoT solutions, where the smart sensors have signal processing capabilities in order to reduce the transmitted data amounts. As a first step, an application specific accelerator for computer vision was implemented. The accelerator was implemented using multicore TTA and programmed with Portable computing language (PoCL) implementation of OpenCL. The accelerator was benchmarked against commercial CPUs and GPUs and was shown to provide higher performance together with significantly lower energy consumption. The simplified TTA architecture of our computer vision accelerator is presented in figure below.

Application specific accelerator for HEVC video coding

In this work, we have accelerated HEVC in-loop filters using energy efficient programmable processor architecture. By assigning in-loop filtering to an appropriate coprocessor instead of a general-purpose processor it is possible to achieve substantial improvements in terms of computation performance and energy consumption. The architecture can be fully programmed using a high level programming language, such as C, which means that it can be used to accelerate also other applications. The system architecture, which is shown below,  is based on transport triggered architecture (TTA) cores which are shown to be energy efficient and have high performance for a wide range of applications.


Hautala I, Boutellier J & Silvén O (2016)

Programmable 28nm coprocessor for HEVC/H.265 in-loop filters. IEEE International Symposium on Circuits and Systems, accepted.

Hautala I, Boutellier J, Hannuksela J & Silvén O (2015)

Programmable low-power multicore coprocessor architecture for HEVC/H.265 in-loop filtering. IEEE Transactions on Circuits and Systems for Video Technology, 25(7):1217-1230.


Last updated: 23.6.2016