Background and Mission
The Circuits and Systems group consists of about 25 researchers working at the Electronics Laboratory of the Department of Electrical Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The main interest of the group is devoted to certain novel devices, circuit topologies and functional units, although the group is also interested in applications, especially in the field of electronic/optoelectronic measurements and telecommunications.
The main research fields are:
- time-to-digital converters and timing circuits
- generation and detection of powerful and high-speed electrical and optical pulses/transients, and breakdown phenomena in semiconductors in general
- development of pulsed time-of-flight laser range finding and Raman spectrometer technologies, especially for industrial applications
- radio telecommunications, including linearization of power amplifiers, AD/DA conversion and baseband blocks, frequency synthesis.
In the following, some details and results of the work of the group are given in selected important research fields.
Time-to-digital converters and optical receiver circuits
A sub-ps-level resolution CMOS time-to-digital converter based on time domain successive approximation interpolation
The proposed time-to-digital converter (TDC) aims at adjustable sub-ps-level resolution with high linearity in the ms-level dynamic range. To achieve sub-ps-level resolution with cyclic time domain successive approximation (CTDSA) within a clock cycle, the propagation delay difference is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance. The TDC uses only a CTDSA as an interpolator with a 5 ns dynamic range within a clock cycle for sub-ps-level resolution and a counter for ms-level dynamic range without a DLL, as shown in Figure 1. The measurement result, i.e. the time interval between the start and stop signals, is obtained by combining the results of the counter (CTR) and the interpolator. The counter gives the number of full clock cycles between the start and stop signals, multiplied by the number of LSBs within the clock cycle.
Figure 1. TDC with ns-level DR & sub-ps-level resolution.
he key functional blocks of the CTDSA architecture of Figure 2 are the two digital-to-time converters (DTC) for binary controlled delay adjustments, the phase detector (PD) for decision-making, and shift register (SREG14) for storing the conversion result. The multiplexers, monostables and DTCs form two loops, highlighted in Figure 2, in which the two signals representing the residue propagate during the cyclic conversion process.
Currently, the layout design of the proposed TDC is in progress. The layout design of the most crucial part, DTC, is in the post layout simulation phase.
Figure 2. 13-bit CTDSA.
Algorithmic time-to-digital converter based on frequency switching
A two-stage TDC is being developed aiming for a single-shot precision close to one picosecond. A coarse time quantization is done by a reference clock counter. The quantization error of the reference clock counter is then measured by two interpolators. These interpolators are based on a cyclic/algorithmic approach, thus they can achieve very high resolution. In each cycle, the time residue is quantized by a ring oscillator counter. The quantization error of the ring oscillator is then amplified by switching the frequency of the ring oscillator. The following amplified time residue is then measured again by the ring oscillator counter. This procedure continues as long as necessary to achieve the desired resolution.
Based on schematic level simulations and Monte Carlo analysis, the peak-to-peak nonlinearity error is expected to be around 2-3 picoseconds. The standard deviation of the nonlinearity error is about 1 ps. Figure 3 shows the simulated nonlinearity errors due to mismatch and process variations.
The layout of the new circuit is currently being designed using a 0.35 µm CMOS process.
Figure 3. Nonlinearity error of the interpolator.
A CMOS time-to-digital converter based on internal averaging
A new digital time-to-digital converter is under development with 65nm CMOS technology. The goal is to reach picosecond-level measurement precision for the time interval between two timing signals, start and stop. The new architecture includes a stabilized delay line, counter, passive time sample generation unit and a total of 128 individual registers for interpolation, see Figure 4. The stabilized delay line creates time samples with 20ps resolution. The delay line uses a successfully tested reference recycling method, which makes the use of a 100MHz reference frequency possible, and decreases the length of the delay line to 16 delay elements. The counter counts the rounds of this delay line between the timing signals and provides a long measurement range. A passive time sample generation unit uses four resistors connected in series, which are added between the delay line delay elements. Four consecutive time samples can be recognized between the resistors when the reference signal propagates in the main delay line. Hence the mean interpolation resolution becomes 20ps/4= 5ps. The timing signal arrival is delayed to 64 different phases, each of which register the prevailing time sample from the passive time sample generator. So, a total 64 different interpolation results are obtained for both start and stop signals. The factors deteriorating the interpolation precision, mainly integral nonlinearity, vary during the 64 consecutive interpolations, and the resulting average error approaches zero when the average interpolation result is calculated. Theoretically, the improvement in precision when using 64 individual interpolators for each timing signal is √64 = 8, which means that precision better than a 1 ps single-shot could be possible. The development is in the schematic design-phase, so the measurement results can be expected by the end of 2014.
Figure 4. Architecture of the CMOS TDC.
An integrated CMOS receiver channel with TDC for pulsed time-of-flight
An integrated receiver channel is under development for a pulsed time-of-flight (TOF) laser radar, based on a 0.35 µm CMOS process. The goal is to integrate a high-performance receiver channel and a multi-channel TDC (time to digital converter) on the same IC chip.
The receiver channel has been designed to cover a wide dynamic range of 1:100 000. The timing walk error (dependence of the timing moment on the pulse amplitude) is compensated for in the time-domain by measuring both the width and the slew-rate of the received pulse echo with a multi-channel TDC. As the relationship between the generated walk error and the pulse width/slew-rate is known in advance (calibration measurement), accurate distance measurement can be done. The operation principle of the compensation method is shown in Figure 5. Timing marks (stop 1 and stop2) are discriminated using a threshold voltage Vth(low). A higher reference level Vth(high) is used to discriminate the timing mark (stop3) for the slew-rate measurement.
Figure 5. The walk compensation principle based on the pulse width and slew-rate measurement.
The block diagram of the receiver channel is shown in Figure 6.
Figure 6. Block diagram of the laser radar receiver channel.
Pulsed time-of-flight ranging based on a digital transient recorder
The sub-ps resolution TDC developed requires a high SNR at the receiver side, which is very often not available, for example for very long distant measurement, or ultra-low power operation. Our other approach for laser ranging is to record the received optical pulse in digital memory as early as possible in the receiver, then to apply various digital filtering and detecting techniques, see Figure 7.
Figure 7. Illustration of time-of-flight measurement based on a digital transient recorder.
Our research suggests using a 2-level comparator in favor of a multi-bit ADC. Statistical analysis of ADCs with random input shows that a comparator introduces only a 20% drop in SNR.
Various digital pulse detection methods have been investigated, and their performances are analytically quantized. An optimal transceiver architecture is suggested which requires narrow optical pulse and matched or derivative matched filter. The relationship between transmitted optical power and energy/measuring time/digital clock speed and measurement resolution/distance is established.
Generation and detection of electrical/optical transients
Improvement in the gain-switched high-energy picosecond laser diode pulse shape using saturable absorber implementation
A saturable absorber (SA), by means of an unpumped section, is introduced in a previously proposed Fabry-Perot semiconductor laser with a strongly asymmetric DH bulk structure and a relatively thick (80 nm) active layer. The focused ion beam technique (FIB) is used here to remove a part of the anode metal contact (Figure 8, inset right). The structure, with a 30 µm long SA, suppresses oscillations at the trailing slope of the optical pulse and decreases the optical pulse width compared to the structure before SA implementation (Figure 9). The improved gain-switched single optical pulse is trailing oscillation free with ~80 ps full width at half maximum (FWHM) and ~35 W peak power, which corresponds to ~3 nJ optical pulse energy. The intensity – time profile was measured with a spectrograph equipped streak camera. The pump current pulse applied here is 17 A in amplitude and 1.3 ns in duration provided by an optimized silicon avalanche transistor based driver circuit (Figure 10) at a pulse repetition rate of 1 kHz. The package is intended for laser ranging and other optoelectronic measurement applications, especially for single photon measurements.
Figure 8. Schematic of the laser diode with the indicated saturable absorber area located close to the laser diode front facet (cavity length: 1.4 mm, oxide stripe width: 128 µm) and a SEM graph of the 30 µm long saturable absorber area implemented by focused ion beam technique (inset, right).
Figure 9. Measured pump current pulse of 17 A in amplitude and 1.3 ns in duration, with a corresponding optical response pulse from a strongly asymmetric DH bulk high-speed laser diode, based on “improved” gain-switching (approx. 850 nm). The optical pulse from the structure before SA implementation (lSA = 0) and with 30 µm long SA (lSA = 30 µm).
Figure 10. Laser diode and driver circuit board (area approx. 1 cm2).
High-speed avalanching BJTs as high-current drivers for LDs and UV LEDs, and as high-power pulsed emitters for sub-THz imaging
For nanosecond/sub-nanosecond pulse durations, the GaAs-based avalanche bipolar junction transistors (ABJTs) suggested, designed and investigated in Electronics Laboratory within the last 15 years, are apparently the best active high-voltage/high-speed switches, but their reproducible technology has been thus far under development, and commercialization of this device still requires significant investments and time. Si ABJT’s have been most frequently used for nanosecond pumping of pulsed laser diodes, but Si avalanche transistors with a switching time of less than 2 ns are missing, and designing of a new generation of Si ABJT’s producing even shorter pulses with a high (1-30 A) current amplitude is a very challenging task that requires deep physical understanding to be achieved for this sophisticated operation mode.
What is peculiar is the fact that a comprehensive physical description of the Si ABJT transient at high current densities was absent until the last decade, and the first reliable 1-D and 2-D description of the process we presented recently. (The point is that only modern numerical methods of physics-based transient modeling allowed the principal features of the old phenomenon to be understood, while rough assumptions utilized in 1950’s -70’s in analytical models led to erroneous conclusions, which remained popular for several decades). Furthermore, despite the age of the phenomenon exceeding half a century, its importance in modern nanosecond and sub-nanosecond optoelectronics applications continues to grow. This makes the task of deep physical investigation of an avalanche switching timely and challenging. We have experimentally proved lately that the parameters of short-pulsing avalanche switching in a Si ABJT cannot be explained (or predicted) without consideration of fairly complicated 3-D transient phenomena. Several interesting findings were made concerning significant and non-monotonic change in the switching size along the emitter-base fingers during fast stage of the switching transient due to two competing physical mechanisms: channel shrinkage and turn-on spread (see Figure 11). Here, of principal importance is the peak current density value, which has to be as high as possible for fast switching with low residual voltage, but at the same time should not exceed the destruction level due to local overheating. Very recently we have additionally shown that 3-D dynamics is of principal importance not only during high-current switching stage, but also during switching delay.
Figure 11. Switching transient (a), current density profiles and (b) normalized current density profiles (c) shown for fast switching stage in a Si avalanche transistor. Instants corresponding to the curves in (b) and (c) are related to the transient in (a) as follows: 1-4.2ns; 2-6.2ns; 3-6.8ns; 4-7.3ns; 5-8.4ns; 6-9.3ns. Curve 7 in (c) shows the shape of the optical excitation. Please note that the normalized curves in (c) first shrink from initial excitation profile (curve 7) to current density profiles 1 and 2, and then spread to profiles 3, 4, 5 and 6. Together with the temporal profile of the collector current (a), the size variations in (c) cause changes in the current density, and the last one controls the switching speed at each particular instant.
The last finding gives an approach to optimal chip design of novel, unique switching devices aiming at 0.2-2 ns range of the current pulse durations with amplitudes ranging from several to a few dozen amperes, see Figure 12. Such miniature, cost-effective devices are missing; demand for such switches is growing, while design principles for those devices have been missing, as well as a physical understanding of their operation. It is worth noting that technologically new devices will fit well to the-state-of-the-art of Si technology, and the physical principles of their operation and corresponding design ideas are the main bottleneck in developing the new generation of Si ABJTs.
Figure 12. Layout of an avalanche transistor (a), and measured radiative recombination pattern (b) which marks the switching channels at short-pulsing mode (2ns/10A/82 pF). (c) and (d) illustrate the reason for the triggering inhomogeneity consisting of crowding of the current of injected electrons near the corners of the emitter-base interface. (c) corresponds to a large radius R of the curvature corresponding to the corners A, B, C, D in (a), and (d) corresponds to the “sharp” corners E and F.
Together with high-current/short pulse generation, a very promising (and the apparently most important) application for the avalanche switching in GaAs BJT is the generation of pulsed broad-band terahertz emission. Periodical nucleation and annihilation of ultra-narrow, powerfully ionizing “collapsing” domains is believed to cause the THz emission observed in our experiments. The task of design, development and investigation of high-power pulsed (ns/sub-ns) emitters for a new generation of active sub-THz imagers should be divided into several directions and stages, and this is the major part of our strategic TEKES project (MIWIM), which starts in 2014. The main direction is the design and development of BJT GaAs-based structures combined with properly designed sub-THz antennas, and using them together with miniature, fast, room-temperature quasi-optical detector based on a Schottky diode. The solution of a large number of the related tasks is underway, and the first laboratory examples of transmission sub-THz imaging utilizing not only transmission intensity, but also propagation delay of the pulses across the object with temporal resolution of ~10-30 ps have been presented in several plenary and invited talks. The results from our first prototypes of millimeter-wave radars are at a very early stage however, before their public release as it concerns various technological and experimental details.
Multiphase time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy
Raman spectroscopy is based on inelastic scattering, or Raman scattering, of monochromatic light, usually from a CW (continuous wave) laser in the visible, near infrared or near ultraviolet range. Unfortunately, the Raman spectrum is masked in most otherwise potential cases by a strong fluorescence background. This is due to the fact that the probability of Raman scattering is much lower than that of fluorescence. As a result, in spite of the obvious advantages of Raman spectroscopy, this strong fluorescence background has so far restricted its use in most potential applications in the fields of the agricultural, food and oil industries, security control and crime investigations, for example.
It is possible to suppress the fluorescence background to a great extent, if intensive short laser pulses are used to illuminate the sample instead of CW radiation, and by recording the sample response only during these short pulses. The suppression is due to the fact that Raman scattering is introduced immediately after the collision between the photons and the sample material, unlike fluorescence, which is emitted after a delay characteristic to the sample. Thus, by “time-gating” the measurement for only the period of the laser pulse, most of the fluorescence is blocked out from the recorded spectrum.
The block diagram of the pulsed Raman spectrometer and the principle of fluorescence suppression are shown in Figure 13. The material to be measured is excited by means of a pulsed laser, emitting short 70-150 ps (FWHM) and spectrally narrow (~0.2 nm) pulses at an average power level of a few mW. The SPADs of the detector array (SPAD-IC) are enabled by the trigger pulse from the pulsed laser just before each laser pulse, and the photons are counted during short time periods (Dt1, Dt2, Dt3, Dt4), in order to suppress the fluorescence and effective dark count rate (DCR).
Figure 13. Block diagram and time gating principle of the proposed Raman spectrometer.
A multiphase time-gated 2*4*128 single photon avalanche diode (SPAD) array has been designed and fabricated in a standard high-voltage 0.35 µm CMOS technology for the above spectrometer. Each of the two columns consists of four parallel connected SPADs. A 50 ps -100 ps time resolving capability can be achieved by using the multiphase time-gated structure. Raman spectra of an olive oil sample are shown in Figure 14, measured with the 2*4*128 SPAD array demonstrating the fluorescence suppression.
Figure. 14. Raman spectra of olive oil with the commercial (red) and our Raman spectroscopy (blue).
A time-gated 4*128 SPAD array with a 3-bit 512 channel flash 80 ps-TDC has been also fabricated in a standard high-voltage 0.35 µm CMOS technology for Raman spectroscopy. In this design, each of four columns works independently so that the dark count rate performance of the active area required can be improved by using separate SPADs in a row, instead of one larger SPAD. Additionally, photons can be detected by all these SPADs separately, and thus a possible noisy detector in a spectral row can be excluded from the final result. The flash type 512 channel TDC measures the arrival time of photons of every pixel (4*128) so that Raman photons and fluorescence photons can be distinguished at each of the spectral points, and thus the level of fluorescence background can be further suppressed.
A third version of the time-gated SPAD array has been also designed with the same technology as the earlier versions, however with a larger array of 16*256 pixels and a 3-bit 256 channel TDC. The resolution of the TDC is approximately 50 ps. The layout of this IC is shown in Figure 15. The design is under fabrication and the tape out date will be at the end of February 2014.
Figure. 15. Layout of the 16*256 SPAD array with 256 channel TDC.
Circuit analysis and linearization techniques
Distortion contribution analysis algorithm VoHB
A general-purpose distortion contribution analysis called VoHB (Volterra on Harmonic Balance) has been under development for a decade, and it is currently available as a plugin for the commercial AWR-Aplac circuit simulator, where it can use all the device models available in Aplac.
VoHB runs at a VCCS (voltage-controlled voltage source) level to be able to calculate frequency-domain mixing effects. Each VCCS is modeled as a polynomial that is fitted using the simulated large-signal spectra obtained directly from harmonic balance simulation. With the help of the polynomial models it is easy to calculate the distortion propagation and band-to-band mixing through the circuit to an arbitrary node. During 2013, the fitting methods were considerably improved.
The first problem comes from the internal structure of many modern device models: they no longer resemble the classical pi model. As the designer needs to know what VCCS or VCQS is causing each contribution, a first attempt was made to canonize the presentation of the results: independent of the actual structure of the transistor device model, its nonlinearities were modeled by one conductive and one capacitive source in both the input and output ports. This gives the designer sufficient information, and is independent of the actual modeling. In a way, this is quite similar to the concept of input-reduced noise contributions.
Another big issue was the reliability of the fitting. It has already been shown that the strength of the polynomial model is sufficient also for highly nonlinear applications, and the effects of frequency domain fitting, scaling and spectral weighting have been verified. Yet, a too narrow data trajectory, when transistor input and output signals look very similar, easily causes the polynomials to have excessive curvature in the operation regime, and this was not satisfactorily solved until 2013.
Quite nonlinear or reactively loaded transistors can usually be fitted using the data available from a normal multi-tone harmonic balance RF simulation. If the device is very linear, or has more than two controlling ports, we need to break the correlation between the input signals used for fitting, and this means running an additional characterization simulation. Here the basic idea is to broaden the output load-line by adding some tones to the output that are not found in the input signal. Signals in the fundamental band broaden the load line, and signals in the 2nd harmonic band can be used to shape the load line asymmetrically so that the drain voltage trajectory is broad enough, but they still avoid reverse biasing of the body diode and operation in the breakdown region. This is illustrated in Figure 16. This task has been done in partial co-operation with Prof. Pedro’s group at University of Aveiro, Portugal.
Figure 16. The effect of fitting range on the shape of the resultsing polynomial modeling. LDMOS Ids-Vds curves with a) a 2-tone test excitation and b) with some fundamental and harmonic power added to the drain voltage.
The design of supply modulated RF transmitters
The work on supply modulated RF transmitters has continued by designing a new supply modulator circuit using the traditional asynchronous hysteretic feedback taken from the current polarity of the assisting linear amplifier, see Figure 17. The circuit has 1.8 W maximum output power, 19 MHz bandwidth and max. 65% power efficiency. The power dissipation and synchronization behavior with the input signal were thoroughly investigated, and a lot of time was spent in minimizing the EMI emissions of the modulator. The modulator was used to test several known predistortion techniques with and without memory, using a linear 1 GHz, 1 W envelope tracking amplifier.
Figure 17. Schematics of the 19 MHz, 1.8 W supply modulator for our envelope tracking test setup.
Biomedical measurements and power management
The design of an integrated, low power 16-channel neural signal recorder / excitation circuit is a co-project with Department of Biophysics, at the University of Oulu. The design was mostly completed during 2013: the power dissipation, bandwidth tuning and noise properties of the receiver channels were solved, but a real-time recording through an SPI serial bus caused some re-thinking, and a 32-sample buffer memory was implemented on the chip. The circuit will be processed in an AMS 0.35 um process in the early months of 2014.
Christian Schuss is doing his PhD on efficient energy harvesting for low power applications. During 2013 he co-operated with University of Graz in optimizing a car-roof photovoltaic energy harvester, and with Department of Information engineering by providing indoor photovoltaic energy harvesting measurements.
Sun Jia is doing her PhD thesis on efficient modeling and power minimization techniques of switched capacitance blocks in AD and DA converters. In 2013, she tested the idea of using passive charge-sharing in speeding up the settling of SC blocks. It appeared that especially the residue amplifiers of a pipeline AD converter can easily be boosted by pre-charging their load capacitances so that passive charge sharing pulls most of the charge from the input capacitors, which effectively bypasses the slew-rate limited settling phase.
Academy of Finland
Ministry of Education and Culture
1 018 000
Duan Guoyong (2013) Three-dimensional effects and surface breakdown addressing efficiency and reliability problems in avalanche bipolar junction transistors. Acta Universitatis Ouluensis. Technica C 444.
P. Keränen, J. Kostamovaara, “Oscillator instability effects in time interval measurement”, IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 60. No. 7, pp. 1776-1786, 2013.
J. Kostamovaara, J. Tenhunen, M. Kögler, I. Nissinen, J. Nissinen, P. Keränen, ”Fluorescence suppression in Raman spectroscopy using a time-gated CMOS SPAD”, Optics Express, Vol 21 Issue 25, pp. 31632 – 31645, 2013.
B. Lanz, S.N. Vainshtein, V.M. Lantratov, N.A. Kalyuzhnyy, S.A. Mintairov and J.T. Kostamovaara, “Picosecond internal Q-switching mode correlates with laser diode breakdown voltage,” Springer, Semiconductors 47, 3, 383-385, 2013.
B. Ryvkin, E. Avrutin, J. Kostamovaara, ”Narrow versus broad asymmetric waveguides for single-mode high-power laser diodes”, Journal of Applied Physics 114, 013104, doi: 10.1063/1.4812571, 2013.
B. Lanz, B. Ryvkin, E. Avrutin, J. Kostamovaara,” Performance improvement by a saturable absorber in gain-switched asymmetric-waveguide laser diodes ”, Optics Express, Vol 21 Issue 24, pp. 29780 – 29791, 2013.
G. Duan, S.N. Vainshtrein, J. T. Kostanmovara, V. E. Zemlyakov, V. I. Egorkin, “Three-dimensional properties of the switching transient in a high-speed avalanche transistor require optimal chip design”, accepted for publication in IEEE Trans. El. Dev., Manuscript ID: TED-2013-10-1314-R.
S. Vainshtein, G. Duan, J. Kostamovaara, “How high-speed transient in a Si avalanche transistor can be improved by smart chip design, Annual Journal of Electronics (ISSN 1314-0078), pp.172-175, 2013.
S. Vainshtein, G. Duan, J. Kostamovaara, “How high-speed transient in a Si avalanche transistor can be improved by smart chip design”, Annual Journal of Electronics (ISSN 1314-0078), pp.172-175, 2013.
S.N. Vainshtein, J.T. Kostamovaara.”Collapsing field domains in electron-hole plasma of GaAs, and examples of the phenomenon application from superfast voltage switch to sub-THz imaging”, Plenary talk at Saratov Fall Meeting - SFM’13 Symposium Optics and Biophotonics (http://sfm.eventry.org/report/671), September 25 - 28, 2013, Saratov, Russia
S.N. Vainshtein, J.T. Kostamovaara. ”Millimeter-wave propagation delay imaging utilizing miniature sub-nanosecond pulsed source.” Invited talk at 6th Finnish-Russian Photonics and Laser Symposium (PALS’2013, www.uef.fi/fi/pals), 3-5 October 2013, Kuopio, Finland
I. Nissinen, J. Nissinen and J. Kostamovaara, ”2×(4×)128 time-gated CMOS single photon avalanche diode line detector with 100 ps resolution for Raman spectroscopy”, Proceedings of the ESSCIRC 2013, September 17-19, Bucharest, Romania, 2013, pp. 291 – 294.
J. Nissinen, J. Kostamovaara, “A 4 a peak current and 2 ns pulse width CMOS laser diode driver for high meas-urement rate applications”, Proceedings of the ESSCIRC 2013, 16-20 September 2013, Bucharest, Romania, p.355 - 358.
I. Nissinen, J. Nissinen and J. Kostamovaara, ”A time-gated 4×128 SPAD array with a 512 channel flash 80 ps-TDC for pulsed Raman spectroscopy”, Proc. of ECCTD’13, 8-12 Sept. 2013, Dresden, Germany, pp. 1-4.
S. Alahdab, A. Mantyniemi, J. Kostamovaara, “A time-to-digital converter (TDC) with a 13-bit cyclic time domain successive approximation interpolator with sub-ps-level resolution using current DAC and differential switch,” Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on , vol., no., pp.828,831, 4-7 Aug. 2013
P. Keränen, J. Kostamovaara, ”Algorithmic Time-to-Digital Converter”, 2013 NORCHIP Conference, Nov. 2013.
T. Rahkonen, J. Aikio, “Analyzing Distortion Contributions in a Complex Device Model”, Compel International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Appearing April 2014
T. Rahkonen, J. Aikio, J. Pedro, “Comparison of Time-Domain and Frequency Domain Polynomial Fitting”, ECCTD 2013 conference, Dresden, September 2013
S. Hietakangas, M. Hietanen, T. Rahkonen, “1.8 W, 19 MHz modulated power supply”, In proc. Norchip 2013 conference, Vilnus, Lithuania, Nov 11-12 2013.
M. Neitola, T. Rahkonen, “Comparison of Static and Memory Predistortion in Envelope Tracking System”, In proc. Norchip 2013 conference Vilnus, Lithuania, Nov 11-12 2013.
J. Aikio, T. Rahkonen, T. Korkala, “Analysis of Band-to-band Mixing Distortion Contributions in Some Usual Circuit Topologies”, In proc. Norchip 2013 conference, Vilnus, Lithuania, Nov 11-12 2013.
S. Jia, T. Rahkonen, “Settling Performance Enhancement by Pre-charging Technique in Switched-Capacitor Circuit”, In proc. Norchip 2013 conference, Vilnus, Lithuania, Nov 11-12 2013.
C. Schuss, T. Rahkonen, “Measurement and Verification of Photovoltaic (PV) Simulation Models”, 2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) . pp. 188-193.
Last updated: 26.2.2015