Thesis defence in the University of Oulu

Doctoral Candidate

Master of Science (Technology) Jia Sun

Faculty and research unit

University of Oulu Graduate School, Faculty of Information Technology and Electrical Engineering, Electronic Circuits and Systems

Field of study

Electrical Engineering

Date and time of the thesis defence

14.11.2019 12:15

Place of the thesis defence

IT115, Linnanmaa

Topic of the dissertation

Speeding up the settling of switched-capacitor amplifier blocks in analog-to-digital converters

Opponent

Professor Mikko Valkama, Tampere university of Technology

Custos

Professor Timo Rahkonen , University of Oulu

Behavioural modelling and speed up analog-to-digital converters

Amplifiers based on coupled capacitances (SC technology) are the most important components of analog-to-digital converters (AD converter) based on CMOS technology. The purpose of this dissertation was to study and model the settling time of SC technology based amplifier circuits, and to find circuit engineering ways to accelerate settling time. One of the biggest problems in SC circuit design is to achieve accurate and fast setup with minimal power consumption. The main results of this work are a number of means that can accelerate the settling of SC-connected amplifiers without increasing their power consumption, or achieve earlier performance with less power consumption. The methods are based on controlling the passive charge distribution of the SC circuit so that the transient in the input node of the amplifier is minimized, so that the amplifier does not drift into the current-limited operating range, but its setting is significantly accelerated. The settling of pipeline residue stages can be speeded up by 30% or saved by 30% power. In a typical delta-sigma modulator, the settling speed-up was implemented by an additional charge pump injection. Both a multi-level and continously controlled injection reduced the power about 40% and 43%,respectively.

Dissertation

Last updated: 8.11.2019