Design of millimeter-wave RF front-ends for phased array communication systems on CMOS SOI
Thesis event information
Date and time of the thesis defence
Place of the thesis defence
L6, University of Oulu, Linnanmaa campus
Topic of the dissertation
Design of millimeter-wave RF front-ends for phased array communication systems on CMOS SOI
Doctoral candidate
Master of Science Mikko Hietanen
Faculty and unit
University of Oulu Graduate School, Faculty of Information Technology and Electrical Engineering, CWC - Radio Technologies
Subject of study
Telecommunications
Opponent
Professor Henrik Sjöland, Lund University (Sweden)
Custos
Professor Aarno Pärssinen, University of Oulu
Radio frequency front-end circuit design on silicon semiconductor teknology for next generation wireless communication systems
This thesis studies radio frequency (RF) front-ends for next-generation wireless communication systems, along with designed prototype circuits. The RF front-end circuit limits both the range and capacity of a wireless link via its output power and receiver sensitivity which dictate the overall performance of a telecommunication system.
A system-level analysis method is presented, which is used to study how carrier frequency, data rate and link range relate to each other within the performance constraints of modern silicon-based semiconductor (CMOS) technology. The results show that the carrier frequency rises nearly linearly with data rate requirements, and that the link range specification determines the system’s power consumption. A significant observation is that the modern CMOS technology can enable wireless links with data rates beyond 100 Gbps (hundred billion bits per second), which the next generation telecommunication networks (6G) are expected to deliver.
Three RF front-end circuits were designed and measured: two at 28 GHz and one for 150 GHz. The first 28 GHz circuit consumes an expeptionally low amount of power in receive mode, and the integrated antenna switch uses minimal amount of area making the circuit manufacturing more cost-effective. The antenna switch enables the utilization of a single antenna for both transmission and reception. The second 28 GHz:n front-end circuit was designed as part of a full transceiver system chip, which has been an important research platform for future phased array system research and development in University of Oulu. The third front-end was designed for 150 GHz to test the CMOS technology limits. Its performance is on par with the best CMOS RF front-ends reported in the literature.
A system-level analysis method is presented, which is used to study how carrier frequency, data rate and link range relate to each other within the performance constraints of modern silicon-based semiconductor (CMOS) technology. The results show that the carrier frequency rises nearly linearly with data rate requirements, and that the link range specification determines the system’s power consumption. A significant observation is that the modern CMOS technology can enable wireless links with data rates beyond 100 Gbps (hundred billion bits per second), which the next generation telecommunication networks (6G) are expected to deliver.
Three RF front-end circuits were designed and measured: two at 28 GHz and one for 150 GHz. The first 28 GHz circuit consumes an expeptionally low amount of power in receive mode, and the integrated antenna switch uses minimal amount of area making the circuit manufacturing more cost-effective. The antenna switch enables the utilization of a single antenna for both transmission and reception. The second 28 GHz:n front-end circuit was designed as part of a full transceiver system chip, which has been an important research platform for future phased array system research and development in University of Oulu. The third front-end was designed for 150 GHz to test the CMOS technology limits. Its performance is on par with the best CMOS RF front-ends reported in the literature.
Last updated: 31.7.2025