CMOS full custom IC layout design

Monday, September 29, 2014 to Thursday, November 13, 2014

 

Infotech Oulu Doctoral Program

Electronics laboratory organizes a postgraduate course on electronics under the following topic "CMOS full custom IC layout design". This course covers the main topics related to CMOS full custom IC layout design, concentration on analog IC design. The targeted audience is integrated circuit designers with little or no previous layout design experience. After the course the students should be able to start layout design autonomously.The course is aimed mainly at post-graduate students but the graduate students having the necessary background are welcome as well.

The planned contents of the course is as follows (subject to changes):

1. Process steps; 2. Device layouts; 3. Matching; 4. Shielding; 5. Substrate isolation; 6. Planarization; 7. ESD; 8. Reliability; 9. Layout design steps; 10. IP floorplanning considerations; 11. IC floorplanning considerations; 12. Layout checks; 13. Bonding, flipchip, WLCSP considerations;L 14. Hands-on training.

The first 4 lectures (4 x 2h) cover the topics from 1) to 13), and remaining 12 lectures (12 x 2h) are reserved for hands-on training in a computer classroom. The training environment consists of Cadence Virtuoso 6.1.5 and hitkit. The course starts in October and continues until mid-December, 2 x 2h per week, from 15:00 to 17:00.

Room: TS136

Date & Time

1) 29.09.14 ma 16.15-18.00  TS136
2) 30.09.14 ti 15.15-17.00  TS136
3) 02.10.14 to 16.15-18.00  TS136
4) 06.10.14 ma 16.15-18.00  TS136
5) 07.10.14 ti 15.15-17.00  TS136
6) 09.10.14 to 16.15-18.00  TS136
7) 13.10.14 ma 16.15-18.00  TS136
8) 14.10.14 ti 15.15-17.00  TS136
9) 16.10.14 to 16.15-18.00  TS136
10) 27.10.14 ma 16.15-18.00  TS136
11) 28.10.14 ti 15.15-17.00  TS136
12) 30.10.14 to 16.15-18.00  TS136
13) 03.11.14 ma 16.15-18.00  TS136
14) 10.11.14 ma 16.15-18.00  TS136
15) 11.11.14 ti 15.15-17.00  TS136
16) 13.11.14 to 16.15-18.00  TS136

The course will be given by adjunct professor,  Dr. Tarmo Ruotsalainen, who is currently working with Ericsson leading an analog IC design team working on full custom analog CMOS circuits for mobile telecommunications applications. Previously he has been working in the University of Oulu, Electronics Laboratory (1987-2000), Nokia Mobile Phones/Nokia (2000-2007), ST-Microelectronics/ST-Ericsson (2007-2013) and Ericsson (2013-present). He has over twenty years of professional experience in various types of full custom analog, high frequency, RF and mixed signal IC projects in designer, architect, manager etc. roles. He has also continued his teaching activities and lectured courses such as Electronic Design II and Electronic Design III in the University of Oulu.

Those interested to participate, please send an email to Dr. Jan Nissinen (firstname.lastname@ee.oulu.fi) by 22nd of September 2014.

More information is available from prof. Juha Kostamovaara.

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Last updated: 19.9.2014