CMOS Full Custom IC Layout Design

Monday, April 4, 2016 to Wednesday, May 25, 2016

 

Infotech Oulu Doctoral Program

CAS research group will organize the following post graduate course (available also for graduate students in electronics with the background of Electronics Design II and III). The course will be lectured by adj.prof. Tarmo Ruotsalainen. Please, register with an email to Jan.nissinen(at)ee.oulu.fi by the 24th of April.

"CMOS Full Custom IC Layout Design"

The course is targeted to students and engineers with little or no previous IC layout design experience. The course covers the basic theory and practical design steps for manual IC layout design. After the course the students should be able to design and verify basic analog and simple digital layouts independently in Cadence Virtuoso environment. The course covers the following topics:

1.Process steps
2.Device layouts
3.Matching
4.Shielding
5.Substrate isolation
6.Planarization
7.ESD
8.Reliability
9.Parasitic capacitances and resistances
10.Layout design steps
11.Layout checks
12.Bonding, flip chip, WLCSP considerations
13.Hands-on training

Lectures and training will be held in TS137 a indicated below:

1) Ma 4.4 15:15 - 17:00
2) Ke 6.4  15:15 - 17:00
3) Ma 11.4 15:15 - 17:00
4) Ke 13.4  15:15 - 17:00
5) Ma 18.4 15:15 - 17:00
6) Ke 20.4  15:15 - 17:00
7) Ma 25.4 15:15 - 17:00
8) Ke 27.4  15:15 - 17:00
9) Ma 2.5 15:15 - 17:00
10) Ke 4.5  15:15 - 17:00
11) Ma 9.5 15:15 - 17:00
12) Ke 11.5  15:15 - 17:00
13) Ma 16.5 15:15 - 17:00
14) Ke 18.5  15:15 - 17:00
15) Ma 23.5 15:15 - 17:00
16) Ke 25.5  15:15 - 17:00

More information: Juha Kostamovaara

Add to calendar

Back to events

Last updated: 17.5.2016