ITEE-DP: CMOS software defined radio transceivers

Tuesday, August 16, 2016 to Thursday, August 18, 2016


Infotech Oulu Doctoral Program

Lecturer: Eric Klumperink, University of Twente, The Netherlands

Time: August 16-18, 2016
Venue: TS137, on-site Registration


Tuesday, 16.8.2016

Wednesday, 17.8.2016

Thursday, 18.8.2016





In all days

Overview of the Course

Wireless communication has become omnipresent (e.g. GSM, Bluetooth, WiFi) and the radio frequency transceiver hardware is commonly co-integrated with digital signal processing functionality on a CMOS “Systems on Chip”. This course reviews architectural innovations in CMOS radio transceivers that happened roughly over the last 2 decades, moving away from traditional narrowband LC-based architectures to more flexible architectures, known under different names like reconfigurable radio transceivers, SAW-less architectures, software defined radio and cognitive radio. This course reviews the motivation for this gradual transition, reviews key technical challenges and discusses several solutions directions that have been proposed over the last two decades. It also indicates recent trends like carrier aggregation, beamforming and full-duplex and related transceiver challenges.

Objectives of the course: After the course, students should be able to:

1) Mention pros and cons of traditional narrowband LC-based band-pass architectures and analyse limitations in achievable selectivity and tuning range for a fixed L and given varactor C-range.

2) Explain why wideband Low Noise Amplifiers with shunt-feedback and/or noise cancellation have become more prevalent and analyse their gain and noise figure

3) Explain how commonly used mixer architectures can be understood in terms of a time-variant linear equivalent circuits and analyse their conversion gain and harmonic mixing properties

4) Explain qualitatively how N-path filters and switch-R-C mixers can achieve high-Q and flexible centre frequency, and analyse their transfer function behaviour in terms of an equivalent Time-Invariant circuit model

5) Explain how component mismatch limits phase accuracy in Multi-Phase Clock Generation and analyse the effect of C-mismatch on phase accuracy when using delay cells or a frequency divider

NOTE: Related to these key goals there will be exercises with LTSPICE simulations


Eric A. M. Klumperink was born on April 4th, 1960, in Lichtenvoorde, The Netherlands. He received the B.Sc. degree from HTS, Enschede, The Netherlands, in 1982. After a short period in industry, he joined the University of Twente in 1984, participating in analog CMOS circuit research resulting in several publications and his Ph.D. thesis "Transconductance Based CMOS Circuits" (1997). In 1998, Eric started as Assistant Professor at the IC-Design Laboratory in Twente and his research focus changed to RF CMOS circuits. In april-august 2001, he extended his RF expertise during a sabbatical at the Ruhr Universitaet in Bochum, Germany. Since 2006, he is an Associate Professor, teaching Analog & RF IC Electronics. Eric participates in the CTIT Research Institute, guiding PhD and MSc projects related to RF CMOS circuit design with focus on Software Defined Radio, Cognitive Radio and Beamforming. He served as an Associate Editor for the IEEE Transactions on Circuits and Systems-II (2006-2007), IEEE Transactions on Circuits and Systems-I (2008-2009) and the IEEE Journal of Solid-State Circuits (2010-2014). Eric is a member of the TPC of the IEEE RFIC Symposium and was a member of ISSCC (2011-2016). Eric served as IEEE SSC Distinguished Lecturer in 2014/2015. He holds 10+ patents, authored and co-authored 150+ internationally refereed journal and conference papers, and was recognized as top ISSCC paper contributor over 1954-2013, contributing more than 20 papers. He is a co-recipient of the ISSCC 2002 and the ISSCC 2009 "Van Vessem Outstanding Paper Award".

Evaluation: the students will be given a list of home work exercises

Credits: 3 ECTS

More information: Aarno Pärssinen

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Last updated: 8.2.2017